Clock signals are used in virtually every integrated circuit (IC) and electronic system to control timing. For example, every time a rising edge occurs on a clock signal, all the flip-flops in a circuit might change signal, the taster the circuit operates. Therefore, where performance is an issue, circuit designers usually prefer to use the fastest available clock that can be supported by the delays on the logic paths through the circuit. In other words, the performance of a circuit is typically limited by the logic delays on the slowest logic path. However, sometimes the longest path delay through the circuit is significantly shorter than the period of the available clock, and the frequency of the available clock becomes the limiting factor.
One way to overcome this limitation is to create from an input clock signal (e.g., a clock signal having an undesirably low clock frequency) a series of phased clock signals that can then be used to clock successive stages of logic. For example, an input clock signal can be used to generate four phased clock signals delayed from the input clock signal by 0, 90, 180, and 270 degrees (i.e., not delayed, delayed by one fourth of an input clock period, delayed by half of an input clock period, and delayed by three fourths of an input clock period, respectively).
Phased clock signals are typically generated using a phase-lock loop (PLL) or delay-lock loop (DLL) circuit. However, PLLs are analog in nature and take a long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are difficult to design, and often are not feasible in a given circuit or system. DLLs can also be very complicated and difficult to design. Additionally, DLLs typically consume a great deal of silicon area. Hence, creating a set of phased clock signals is often not feasible using known circuits and methods.
Therefore, it is desirable to provide circuits and methods that enable a circuit designer to create a series of phased clock signals from an input clock signal, using a fairly simple circuit that consumes a relatively small amount of silicon area. Preferably, such circuits and methods can optionally be implemented using the logic resources included in a programmable logic device (PLD).